TC7WPN3125FK
CMOS Digital Integrated Circuits
Silicon Monolithic
TC7WPN3125FK
1. Functional Description
•
Low-Voltage, Low-Power 2-Bit Dual-Supply Bus Buffer
2. General
The TC7WPN3125FK is a dual supply, advanced high-speed CMOS 2-bit dual supply voltage interface bus buffer
fabricated with silicon gate CMOS technology.
It is also designed with over voltage tolerant inputs and outputs up to 3.6 V. Designed for use as an interface
between a 1.2-V, 1.5-V, 1.8-V, or 2.5-V bus and a 1.8-V, 2.5-V or 3.6-V bus in mixed 1.2-V, 1.5-V, 1.8-V or 2.5-V/1.8V, 2.5-V or 3.6-V supply systems.
The A-input interfaces with the 1.2-V, 1.5-V, 1.8-V or 2.5-V bus, the B-output with the 1.8-V, 2.5-V, 3.3-V bus.
The enable input OE can be used to disable the device so that the signal lines are effectively isolated.
All inputs are equipped with protection circuits against static discharge or transient excess voltage.
3. Features (Note)
(1)
Wide operating temperature range: Topr = -40 to 125 � (Note 1)
(2)
Operating voltage: 1.2 V to 1.8 V / 1.2 V to 2.5 V / 1.2 V to 3.3 V / 1.5 V to 2.5 V
(3)
High-speed operation: tpd = 13.7 ns (max) (VCCA = 2.5 ± 0.2 V, VCCB = 3.3 ± 0.3 V)
1.5 V to 3.3 V / 1.8 V to 2.5 V / 1.8 V to 3.3 V / 2.5 V to 3.3 V
tpd = 14.8 ns (max) (VCCA = 1.8 ± 0.15 V, VCCB = 3.3 ± 0.3 V)
tpd = 16.0 ns (max) (VCCA = 1.5 ± 0.1 V, VCCB = 3.3 ± 0.3 V)
tpd = 29 ns (max) (VCCA = 1.2 ± 0.1 V, VCCB = 3.3 ± 0.3 V)
tpd = 18.5 ns (max) (VCCA = 1.8 ± 0.15 V, VCCB = 2.5 ± 0.2 V)
tpd = 19.7 ns (max) (VCCA = 1.5 ± 0.1 V, VCCB = 2.5 ± 0.2 V)
tpd = 33 ns (max) (VCCA = 1.2 ± 0.1 V, VCCB = 2.5 ± 0.2 V)
tpd = 43 ns (max) (VCCA = 1.2 ± 0.1 V, VCCB = 1.8 ± 0.15 V)
(4)
Output current: |IOHB|/IOLB = 3 mA (min) (VCCB = 3.0 V)
|IOHB|/IOLB = 2 mA (min) (VCCB = 2.3 V)
|IOHB|/IOLB = 0.5 mA (min) (VCCB = 1.65 V)
(5)
Ultra-small package: US8
(6)
Low power dissipation: By using the new circuit, the power consumption is reduced
significantly when OE = "H".
Suitable for battery-driven applications such as PDAs and cellular phones.
(7)
Floating of A-bus is permitted (when OE = "H").
(8)
3.6 V tolerance and power-down protection are provided to all inputs and outputs.
Note: Do not apply a signal to any bus pins when it is in the output mode. Damage may result.
Note 1: For devices with the ordering part number ending in (CT. Topr = -40 to 85 � for the other devices.
Start of commercial production
2020-12
©2020-2021
Toshiba Electronic Devices & Storage Corporation
1
2021-07-21
Rev.1.0
TC7WPN3125FK
4. Packaging
US8
5. Pin Assignment
©2020-2021
Toshiba Electronic Devices & Storage Corporation
2
2021-07-21
Rev.1.0
TC7WPN3125FK
6. Truth Table
Input
OE
X:
Z:
Input
A1,A2
Outputs
B1,B2
L
L
L
L
H
H
H
X
Z
Don't care
High impedance
7. Block Diagram
©2020-2021
Toshiba Electronic Devices & Storage Corporation
3
2021-07-21
Rev.1.0
TC7WPN3125FK
8. Absolute Maximum Ratings (Note) (Unless otherwise specified, T a = 25 �)
Characteristics
Supply voltage
Symbol
Note
Rating
Unit
VCCA
(Note 1)
-0.5 to 4.6
V
VCCB
Input voltage (An, OE)
-0.5 to 4.6
VIN
Output voltage (Bn)
VOUTB
Input diode current
IIK
Output diode current
IOK
-0.5 to 4.6
V
(Note 2)
-0.5 to 4.6
V
(Note 3)
-0.5 to VCCB + 0.5
(Note 4)
-50
mA
±50
mA
Output current
IOUTB
±6
mA
VCC/ground current per supply pin
ICCA
±25
mA
ICCB
±50
Power dissipation
PD
200
mW
Storage temperature
Tstg
-65 to 150
�
Note:
Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even
destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report
and estimated failure rate, etc).
Note 1: Don't supply a voltage to VCCB pin when VCCA is in the OFF state.
Note 2: Output in OFF state.
Note 3: High (H) or Low (L) state. IOUT absolute maximum rating must be observed.
Note 4: VOUT < GND, VOUT > VCC
9. Operating Ranges (Note)
Characteristics
Supply voltage
Symbol
Note
Test Condition
VCCA
(Note 1)
�
VCCB
Input voltage (An, OE)
VOUTB
Output current (Bn)
IOUTB
Unit
1.1 to 2.7
V
1.65 to 3.6
VIN
Output voltage (Bn)
Rating
(Note 2)
�
0 to 3.6
V
�
0 to 3.6
V
(Note 3)
0 to VCCB
VCCB = 3.0 to 3.6 V
±3
VCCB = 2.3 to 2.7 V
VCCB = 1.65 to 1.95 V
Operating temperature
Topr
(Note 4)
�
(Note 5)
Input rise and fall times
dt/dv
mA
±2
±0.5
-40 to 125
�
-40 to 85
VIN = 0.8 to 2.0 V, VCCA = 2.5 V,
VCCB = 3.0 V
0 to 10
ns/V
Note:
The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either VCC or GND.
Note 1: Don't use at VCCA > VCCB.
Note 2: Output in OFF state.
Note 3: High (H) or Low (L) state.
Note 4: For devices with the ordering part number ending in (CT.
Note 5: For devices except those with the ordering part number ending in (CT.
©2020-2021
Toshiba Electronic Devices & Storage Corporation
4
2021-07-21
Rev.1.0
TC7WPN3125FK
10. Electrical Characteristics
10.1. DC Characteristics
10.1.1. 1.1 V ≤ V CCA ≤ 2.7 V, 1.65 V < V CCB ≤ 3.6 V
(Unless otherwise specified, T a = -40 to 85 �)
Characteristics
High-level input voltage
Symbol
Test Condition
VCCA (V)
VIHA VIN
Min
Max
Unit
1.1 ≤ VCCA ≤ 1.4 1.65 to 3.6
0.65×
VCCA
�
V
1.4 ≤ VCCA ≤ 1.65 1.65 to 3.6
0.65×
VCCA
�
1.65 ≤ VCCA ≤ 2.3 2.3 to 3.6
0.65×
VCCA
�
2.3 ≤ VCCA ≤ 2.7
Low-level input voltage
High-level output voltage
Low-level output voltage
3-state output OFF-state
leakage current
Input leakage current
Power-off leakage current
Quiescent supply current
2.7 to 3.6
1.6
�
1.1 ≤ VCCA ≤ 1.4 1.65 to 3.6
�
0.3×
VCCA
1.4 ≤ VCCA ≤ 1.65 1.65 to 3.6
�
0.3×
VCCA
1.65 ≤ VCCA ≤ 2.3 2.3 to 3.6
�
0.35×
VCCA
2.3 ≤ VCCA ≤ 2.7
2.7 to 3.6
�
0.7
IOHB = -100 µA
1.1 to 2.7
1.65 to 3.6
VCCB
-0.2
�
IOHB = -0.5 mA
1.1 to 1.65
1.65
1.25
�
IOHB = -2 mA
1.1 to 2.3
2.3
1.7
�
IOHB = -3 mA
1.1 to 2.7
3.0
2.2
�
IOLB = 100 µA
1.1 to 2.7
1.65 to 3.6
�
0.2
IOLB = 0.5 mA
1.1 to 1.65
1.65
�
0.3
IOLB = 2 mA
1.1 to 2.3
2.3
�
0.6
IOLB = 3 mA
1.1 to 2.7
3.0
�
0.55
1.1 to 2.7
1.65 to 3.6
�
±2.0
µA
VILA VIN
VOHB An = VIH
VOLB An = VIL
IOZB An = VIHA or VILA
Bn = 0 to 3.6 V
IIN
VCCB (V)
VIN = 0 to 3.6 V
V
V
V
1.1 to 2.7
1.65 to 3.6
�
±1.0
µA
IOFF1 VIN, Bn = 0 to 3.6 V
0
0
�
2.0
µA
IOFF2 OE = VCCA
An, Bn = 0 to 3.6 V
I
1.1 to 2.7
0
�
2.0
OFF3
1.1 to 2.7
Open
�
2.0
ICCA VIN = VCCA or GND
1.1 to 2.7
1.65 to 3.6
�
2.0
ICCB VIN = VCCA or GND
1.1 to 2.7
1.65 to 3.6
�
2.0
ICCA VCCA ≤ VIN ≤ 3.6 V
1.1 to 2.7
1.65 to 3.6
�
±2.0
ICCB VIN = VCCA
VCCB ≤ Bn ≤ 3.6 V
1.1 to 2.7
1.65 to 3.6
�
±2.0
©2020-2021
Toshiba Electronic Devices & Storage Corporation
5
µA
2021-07-21
Rev.1.0
TC7WPN3125FK
10.1.2. 1.1 V ≤ V CCA ≤ 2.7 V, 1.65 V < V CCB ≤ 3.6 V
(Unless otherwise specified, T a = -40 to 125 �)
Characteristics
High-level input voltage
Low-level input voltage
Symbol
Test Condition
VCCA (V)
VIHA VIN
VILA VIN
VCCB (V)
Min
Max
Unit
1.1 ≤ VCCA ≤ 1.4 1.65 to 3.6
0.65×
VCCA
�
V
1.4 ≤ VCCA ≤ 1.65 1.65 to 3.6
0.65×
VCCA
�
1.65 ≤ VCCA ≤ 2.3 2.3 to 3.6
0.65×
VCCA
�
2.3 ≤ VCCA ≤ 2.7 2.7 to 3.6
1.6
�
1.1 ≤ VCCA ≤ 1.4 1.65 to 3.6
�
0.3×
VCCA
1.4 ≤ VCCA ≤ 1.65 1.65 to 3.6
�
0.3×
VCCA
1.65 ≤ VCCA ≤ 2.3 2.3 to 3.6
�
0.35×
VCCA
2.3 ≤ VCCA ≤ 2.7 2.7 to 3.6
High-level output voltage
Low-level output voltage
3-state output OFF-state
leakage current
Input leakage current
Power-off leakage current
Quiescent supply current
VOHB An = VIH
VOLB An = VIL
�
0.7
IOHB = -100 µA
1.1 to 2.7
1.65 to 3.6
VCCB
-0.2
�
IOHB = -0.5 mA
1.1 to 1.65
1.65
1.15
�
IOHB = -2 mA
1.1 to 2.3
2.3
1.6
�
IOHB = -3 mA
1.1 to 2.7
3.0
2.0
�
IOLB = 100 µA
1.1 to 2.7
1.65 to 3.6
�
0.2
IOLB = 0.5 mA
1.1 to 1.65
1.65
�
0.45
IOLB = 2 mA
1.1 to 2.3
2.3
�
0.8
IOLB = 3 mA
1.1 to 2.7
3.0
�
0.8
1.1 to 2.7
1.65 to 3.6
�
±20.0
µA
IOZB An = VIHA or VILA
Bn = 0 to 3.6 V
IIN
V
VIN = 0 to 3.6 V
V
V
1.1 to 2.7
1.65 to 3.6
�
±10.0
µA
IOFF1 VIN, Bn = 0 to 3.6 V
0
0
�
20.0
µA
IOFF2 OE = VCCA
An, Bn = 0 to 3.6 V
I
1.1 to 2.7
0
�
20.0
OFF3
1.1 to 2.7
Open
�
20.0
ICCA VIN = VCCA or GND
1.1 to 2.7
1.65 to 3.6
�
20.0
ICCB VIN = VCCA or GND
1.1 to 2.7
1.65 to 3.6
�
20.0
ICCA VCCA ≤ VIN ≤ 3.6 V
1.1 to 2.7
1.65 to 3.6
�
±20.0
ICCB VIN = VCCA
VCCB ≤ Bn ≤ 3.6 V
1.1 to 2.7
1.65 to 3.6
�
±20.0
©2020-2021
Toshiba Electronic Devices & Storage Corporation
6
µA
2021-07-21
Rev.1.0
TC7WPN3125FK
10.2. AC Characteristics
10.2.1. V CCA = 2.5 ± 0.2 V, V CCB = 3.3 ± 0.3 V
(Unless otherwise specified, T a = -40 to 85 �, Input: t r = t f = 2.0 ns)
Characteristics
Symbol
Note
Test Condition
Min
Max
Unit
ns
Propagation delay time (An → Bn)
tPLH/tPHL
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
13.7
3-state output enable time (OE → Bn)
tPZL/tPZH
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
16.6
3-state output disable time (OE → Bn)
tPLZ/tPHZ
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
7.2
�
0.5
Output skew
tosLH/tosHL
(Note 1)
ns
Note 1: Parameter guaranteed by design. (tosLH = |tPLHm-tPLHn|, tosHL = |tPHLm-tPHLn|)
10.2.2. V CCA = 2.5 ± 0.2 V, V CCB = 3.3 ± 0.3 V
(Unless otherwise specified, T a = -40 to 125 �, Input: t r = t f = 2.0 ns)
Characteristics
Symbol
Note
Test Condition
Min
Max
Unit
ns
Propagation delay time (An → Bn)
tPLH/tPHL
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
14.7
3-state output enable time (OE → Bn)
tPZL/tPZH
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
18.5
3-state output disable time (OE → Bn)
tPLZ/tPHZ
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
8.1
�
1.0
ns
Min
Max
Unit
ns
Output skew
tosLH/tosHL
(Note 1)
Note 1: Parameter guaranteed by design. (tosLH = |tPLHm-tPLHn|, tosHL = |tPHLm-tPHLn|)
10.2.3. V CCA = 1.8 ± 0.15 V, V CCB = 3.3 ± 0.3 V
(Unless otherwise specified, T a = -40 to 85 �, Input: t r = t f = 2.0 ns)
Characteristics
Symbol
Note
Test Condition
Propagation delay time (An → Bn)
tPLH/tPHL
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
14.8
3-state output enable time (OE → Bn)
tPZL/tPZH
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
18.9
3-state output disable time (OE → Bn)
tPLZ/tPHZ
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
8.7
�
0.5
Output skew
tosLH/tosHL
(Note 1)
ns
Note 1: Parameter guaranteed by design. (tosLH = |tPLHm-tPLHn|, tosHL = |tPHLm-tPHLn|)
10.2.4. V CCA = 1.8 ± 0.15 V, V CCB = 3.3 ± 0.3 V
(Unless otherwise specified, T a = -40 to 125 �, Input: t r = t f = 2.0 ns)
Characteristics
Symbol
Note
Test Condition
Min
Max
Unit
ns
Propagation delay time (An → Bn)
tPLH/tPHL
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
15.8
3-state output enable time (OE → Bn)
tPZL/tPZH
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
20.5
3-state output disable time (OE → Bn)
tPLZ/tPHZ
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
9.5
�
1.0
Output skew
tosLH/tosHL
(Note 1)
ns
Note 1: Parameter guaranteed by design. (tosLH = |tPLHm-tPLHn|, tosHL = |tPHLm-tPHLn|)
©2020-2021
Toshiba Electronic Devices & Storage Corporation
7
2021-07-21
Rev.1.0
TC7WPN3125FK
10.2.5. V CCA = 1.5 ± 0.1 V, V CCB = 3.3 ± 0.3 V
(Unless otherwise specified, T a = -40 to 85 �, Input: t r = t f = 2.0 ns)
Characteristics
Symbol
Note
Test Condition
Min
Max
Unit
ns
Propagation delay time (An → Bn)
tPLH/tPHL
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
16.0
3-state output enable time (OE → Bn)
tPZL/tPZH
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
22.8
3-state output disable time (OE → Bn)
tPLZ/tPHZ
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
10.2
�
1.5
Output skew
tosLH/tosHL
(Note 1)
ns
Note 1: Parameter guaranteed by design. (tosLH = |tPLHm-tPLHn|, tosHL = |tPHLm-tPHLn|)
10.2.6. V CCA = 1.5 ± 0.1 V, V CCB = 3.3 ± 0.3 V
(Unless otherwise specified, T a = -40 to 125 �, Input: t r = t f = 2.0 ns)
Characteristics
Symbol
Note
Test Condition
Min
Max
Unit
ns
Propagation delay time (An → Bn)
tPLH/tPHL
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
17.0
3-state output enable time (OE → Bn)
tPZL/tPZH
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
23.4
3-state output disable time (OE → Bn)
tPLZ/tPHZ
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
10.5
�
2.0
ns
Min
Max
Unit
ns
Output skew
tosLH/tosHL
(Note 1)
Note 1: Parameter guaranteed by design. (tosLH = |tPLHm-tPLHn|, tosHL = |tPHLm-tPHLn|)
10.2.7. V CCA = 1.2 ± 0.1 V, V CCB = 3.3 ± 0.3 V
(Unless otherwise specified, T a = -40 to 85 �, Input: t r = t f = 2.0 ns)
Characteristics
Symbol
Note
Test Condition
Propagation delay time (An → Bn)
tPLH/tPHL
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
29
3-state output enable time (OE → Bn)
tPZL/tPZH
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
63
3-state output disable time (OE → Bn)
tPLZ/tPHZ
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
23
�
1.5
Output skew
tosLH/tosHL
(Note 1)
ns
Note 1: Parameter guaranteed by design. (tosLH = |tPLHm-tPLHn|, tosHL = |tPHLm-tPHLn|)
10.2.8. V CCA = 1.2 ± 0.1 V, V CCB = 3.3 ± 0.3 V
(Unless otherwise specified, T a = -40 to 125 �, Input: t r = t f = 2.0 ns)
Characteristics
Symbol
Note
Test Condition
Min
Max
Unit
ns
Propagation delay time (An → Bn)
tPLH/tPHL
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
29
3-state output enable time (OE → Bn)
tPZL/tPZH
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
63
3-state output disable time (OE → Bn)
tPLZ/tPHZ
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
23
�
2.0
Output skew
tosLH/tosHL
(Note 1)
ns
Note 1: Parameter guaranteed by design. (tosLH = |tPLHm-tPLHn|, tosHL = |tPHLm-tPHLn|)
©2020-2021
Toshiba Electronic Devices & Storage Corporation
8
2021-07-21
Rev.1.0
TC7WPN3125FK
10.2.9. V CCA = 1.8 ± 0.15 V, V CCB = 2.5 ± 0.2 V
(Unless otherwise specified, T a = -40 to 85 �, Input: t r = t f = 2.0 ns)
Characteristics
Symbol
Note
Test Condition
Min
Max
Unit
ns
Propagation delay time (An → Bn)
tPLH/tPHL
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
18.5
3-state output enable time (OE → Bn)
tPZL/tPZH
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
23.6
3-state output disable time (OE → Bn)
tPLZ/tPHZ
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
6.9
�
0.5
Output skew
tosLH/tosHL
(Note 1)
ns
Note 1: Parameter guaranteed by design. (tosLH = |tPLHm-tPLHn|, tosHL = |tPHLm-tPHLn|)
10.2.10. V CCA = 1.8 ± 0.15 V, V CCB = 2.5 ± 0.2 V
(Unless otherwise specified, T a = -40 to 125 �, Input: t r = t f = 2.0 ns)
Characteristics
Symbol
Note
Test Condition
Min
Max
Unit
ns
Propagation delay time (An → Bn)
tPLH/tPHL
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
19.9
3-state output enable time (OE → Bn)
tPZL/tPZH
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
25.8
3-state output disable time (OE → Bn)
tPLZ/tPHZ
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
7.8
�
1.0
ns
Min
Max
Unit
ns
Output skew
tosLH/tosHL
(Note 1)
Note 1: Parameter guaranteed by design. (tosLH = |tPLHm-tPLHn|, tosHL = |tPHLm-tPHLn|)
10.2.11. V CCA = 1.5 ± 0.1 V, V CCB = 2.5 ± 0.2 V
(Unless otherwise specified, T a = -40 to 85 �, Input: t r = t f = 2.0 ns)
Characteristics
Symbol
Note
Test Condition
Propagation delay time (An → Bn)
tPLH/tPHL
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
19.7
3-state output enable time (OE → Bn)
tPZL/tPZH
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
26.6
3-state output disable time (OE → Bn)
tPLZ/tPHZ
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
8.3
�
1.5
Output skew
tosLH/tosHL
(Note 1)
ns
Note 1: Parameter guaranteed by design. (tosLH = |tPLHm-tPLHn|, tosHL = |tPHLm-tPHLn|)
10.2.12. V CCA = 1.5 ± 0.1 V, V CCB = 2.5 ± 0.2 V
(Unless otherwise specified, T a = -40 to 125 �, Input: t r = t f = 2.0 ns)
Characteristics
Symbol
Note
Test Condition
Min
Max
Unit
ns
Propagation delay time (An → Bn)
tPLH/tPHL
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
20.8
3-state output enable time (OE → Bn)
tPZL/tPZH
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
27.9
3-state output disable time (OE → Bn)
tPLZ/tPHZ
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
8.6
�
2.0
Output skew
tosLH/tosHL
(Note 1)
ns
Note 1: Parameter guaranteed by design. (tosLH = |tPLHm-tPLHn|, tosHL = |tPHLm-tPHLn|)
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10.2.13. V CCA = 1.2 ± 0.1 V, V CCB = 2.5 ± 0.2 V
(Unless otherwise specified, T a = -40 to 85 �, Input: t r = t f = 2.0 ns)
Characteristics
Symbol
Note
Test Condition
Min
Max
Unit
ns
Propagation delay time (An → Bn)
tPLH/tPHL
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
33
3-state output enable time (OE → Bn)
tPZL/tPZH
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
66
3-state output disable time (OE → Bn)
tPLZ/tPHZ
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
20
�
1.5
Output skew
tosLH/tosHL
(Note 1)
ns
Note 1: Parameter guaranteed by design. (tosLH = |tPLHm-tPLHn|, tosHL = |tPHLm-tPHLn|)
10.2.14. V CCA = 1.2 ± 0.1 V, V CCB = 2.5 ± 0.2 V
(Unless otherwise specified, T a = -40 to 125 �, Input: t r = t f = 2.0 ns)
Characteristics
Symbol
Note
Test Condition
Min
Max
Unit
ns
Propagation delay time (An → Bn)
tPLH/tPHL
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
33
3-state output enable time (OE → Bn)
tPZL/tPZH
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
66
3-state output disable time (OE → Bn)
tPLZ/tPHZ
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
20
�
2.0
ns
Min
Max
Unit
ns
Output skew
tosLH/tosHL
(Note 1)
Note 1: Parameter guaranteed by design. (tosLH = |tPLHm-tPLHn|, tosHL = |tPHLm-tPHLn|)
10.2.15. V CCA = 1.2 ± 0.1 V, V CCB = 1.8 ± 0.15 V
(Unless otherwise specified, T a = -40 to 85 �, Input: t r = t f = 2.0 ns)
Characteristics
Symbol
Note
Test Condition
Propagation delay time (An → Bn)
tPLH/tPHL
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
43
3-state output enable time (OE → Bn)
tPZL/tPZH
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
78
3-state output disable time (OE → Bn)
tPLZ/tPHZ
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
20
�
1.5
Output skew
tosLH/tosHL
(Note 1)
ns
Note 1: Parameter guaranteed by design. (tosLH = |tPLHm-tPLHn|, tosHL = |tPHLm-tPHLn|)
10.2.16. V CCA = 1.2 ± 0.1 V, V CCB = 1.8 ± 0.15 V
(Unless otherwise specified, T a = -40 to 125 �, Input: t r = t f = 2.0 ns)
Characteristics
Symbol
Note
Test Condition
Min
Max
Unit
ns
Propagation delay time (An → Bn)
tPLH/tPHL
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
43
3-state output enable time (OE → Bn)
tPZL/tPZH
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
78
3-state output disable time (OE → Bn)
tPLZ/tPHZ
See Fig. 11.1, 12.1
Table 11.1.1, 11.1.2, 12.1.1
1.0
20
�
2.0
Output skew
tosLH/tosHL
(Note 1)
ns
Note 1: Parameter guaranteed by design. (tosLH = |tPLHm-tPLHn|, tosHL = |tPHLm-tPHLn|)
©2020-2021
Toshiba Electronic Devices & Storage Corporation
10
2021-07-21
Rev.1.0
TC7WPN3125FK
10.3. Capacitive Characteristics (Unless otherwise specified, T a = 25 �)
Characteristics
Input capacitance
Symbol
Note
CIN
Output capacitance
COUT
Power dissipation
capacitance
CPDA
CPDB
VCCA (V) VCCB(V)
Typ.
Unit
An,OE
2.5
3.3
7
pF
Bn
2.5
3.3
8
pF
(Note 1) OE = "L"
2.5
3.3
3
pF
(Note 1) OE = "H"
2.5
3.3
0
(Note 1) OE = "L"
2.5
3.3
13
(Note 1) OE = "H"
2.5
3.3
0
Note 1: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current
consumption without load. Average operating current can be obtained by the equation.
ICC(opr) = CPD × VCC × fIN + ICC/2 (per bit)
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11. AC Test Circuit
Fig. 11.1
Table 11.1.1
AC Test Circuit
Parameter for AC Test Circuit
Parameter
Switch
tPLH, tPHL
Open
tPLZ, tPZL
VCCB
tPHZ, tPZH
GND
Table 11.1.2
Parameter for AC Test Circuit
Symbol
VCCB = 3.3 ± 0.3 V
VCCB = 2.5 ± 0.2 V
VCCB = 1.8 ± 0.15 V
RL
1 kΩ
1 kΩ
CL
30 pF
30 pF
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Toshiba Electronic Devices & Storage Corporation
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Rev.1.0
TC7WPN3125FK
12. AC Waveform
Fig. 12.1
Fig. 12.2
Table 12.1.1
t PLH , t PHL
t PLZ , t PHZ , t PZL, t PZH
AC Waveform Symbols
VCC = 2.5 ± 0.2 V
VCC = 1.8 ± 0.15 V
VCC = 1.5 ± 0.1 V
VCC = 1.2 ± 0.1 V
Symbol
VCC = 3.3 ± 0.3 V
VIH
�
VCCA
VCCA
VIM
�
VCCA/2
VCCA/2
VOM
VOH/2
VOH/2
�
VX
VOL + 0.3 V
VOL + 0.15 V
�
VY
VOH - 0.3 V
VOH - 0.15 V
�
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Toshiba Electronic Devices & Storage Corporation
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Package Dimensions
Unit: mm
Weight: 0.01 g (typ.)
Package Name(s)
JEDEC: SOT-765
Nickname: US8
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Toshiba Electronic Devices & Storage Corporation
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